View X28HT010W_1337152.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
X28C010, X28HT010
Data Sheet February 12, 2007 FN8105.1
5V, Byte Alterable EEPROM
The Intersil X28C010/X28HT010 is a 128K x 8 EEPROM, fabricated with Intersil's proprietary, high performance, floating gate CMOS technology. Like all Intersil programmable non-volatile memories, the X28C010/X28HT010 is a 5V only device. The X28C010/X28HT010 features the JEDEC approved pin out for byte-wide memories, compatible with industry standard EEPROMs. The X28C010/X28HT010 supports a 256-byte page write operation, effectively providing a 19s/byte write cycle and enabling the entire memory to be typically written in less than 2.5 seconds. The X28C010/X28HT010 also features DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28C010/X28HT010 supports Software Data Protection option. Intersil EEPROMs are designed and tested for applications requiring extended endurance. Data retention is specified to be greater than 100 years.
Features
* Access time: 120ns * Simple byte and page write - Single 5V supply - No external high voltages or VPP control circuits - Self-timed * No erase before write * No complex programming algorithms * No overerase problem * Low power CMOS - Active: 50mA - Standby: 500A * Software data protection - Protects data against system level inadvertent writes * High speed page write capability * Highly reliable Direct WriteTM cell - Endurance: 100,000 write cycles - Data retention: 100 years * Early end of write detection - DATA polling - Toggle bit polling * X28HT010 is fuly functional @ +175C
Pinouts
CERDIP Flat Pack SOIC (R)
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X28C010 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
A1 13 A2 12 A4 10 8 A6 A12
PGA
I/O0 I/O2 I/O 3 I/O5 I/O6 15 17 19 21 22 A0 14 A3 11 9 7 A5 A7 A15 A 16 NC 2 NC 3 VCC NC 36 34 NC 1 WE 35 CE I/O1 VSS I/O4 I/O7 16 18 20 23 24 OE A10 26 25
A7 A6 A5 A4 A3 A2 A1 A0 I/O 0
EXTENDED LCC
A12 A15 A16 NC VCC 432 1 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE I/O7 WE NC
32 31 30
X28C010 (Bottom View)
A11 27 A8 29 NC 32 NC 33
A9 28 A 13 30 A 14 31
X28C010 (Top View)
6
5
14 15 16 17 18 19 20 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6
4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X28C010, X28HT010 Ordering Information
PART NUMBER X28C010D-12 X28C010D-15 X28C010DI X28C010DI-12 X28C010DI-15 X28C010DM X28C010DM-12 X28C010DM-15 X28C010DMB-12 X28C010DMB-15 X28C010DMB-20 X28C010FI-12 X28C010FI-15 X28C010FI-20 X28C010FM X28C010FM-12 X28C010FMB-12 X28C010FMB-15 X28C010K-25 X28C010KM-12 X28C010KM-25 X28C010KMB-12 X28C010KMB-15 X28C010NM-12 X28C010NM-15 X28C010NMB-12 X28C010NMB-15 X28C010RI-12 X28C010RI-20 X28C010RI-20T1 X28C010RM-15 X28C010RMB-25 X28HT010W PART MARKING X28C010D-12 X28C010D-15 X28C010DI X28C010DI-12 X28C010DI-15 X28C010DM X28C010DM-12 X28C010DM-15 C X28C010DMB-12 C X28C010DMB-15 C X28C010DMB-20 X28C010FI-12 X28C010FI-15 X28C010FI-20 X28C010FM X28C010FM-12 C X28C010FMB-12 C X28C010FMB-15 X28C010K-25 X28C010KM-12 X28C010KM-25 C X28C010KMB-12 C X28C010KMB-15 X28C010NM-12 X28C010NM-15 C X28C010NMB-12 C X28C010NMB-15 X28C010RI-12 X28C010RI-20 X28C010RI-20 X28C010RM-15 C X28C010RMB-25 ACCESS TIME 120ns 150ns 120ns 150ns 120ns 150ns 120ns 150ns 200ns 120ns 150ns 200ns 120ns 120ns 150ns 250ns 120ns 250ns 120ns 150ns 120ns 150ns 120ns 150ns 120ns 200ns 200ns 150ns 250ns 200ns TEMP RANGE (C) 0 to +70 0 to +70 -40 to +85 -40 to +85 -40 to +85 -55 to +125 -55 to +125 -55 to +125 MIL-STD-883 MIL-STD-883 MIL-STD-883 -40 to +85 -40 to +85 -40 to +85 -55 to +125 -55 to +125 MIL-STD-883 MIL-STD-883 0 to +70 -55 to +125 -55 to +125 MIL-STD-883 MIL-STD-883 -55 to +125 -55 to +125 MIL-STD-883 MIL-STD-883 -40 to +85 -40 to +85 -40 to +85 -55 to +125 MIL-STD-883 -40 to +175 PACKAGE 32-Ld Cerdip 32-Ld Cerdip 32-Ld Cerdip 32-Ld Cerdip 32-Ld Cerdip 32-Ld Cerdip 32-Ld Cerdip 32-Ld Cerdip 32-Ld Cerdip 32-Ld Cerdip 32-Ld Cerdip 32-Ld Flat Pack 32-Ld Flat Pack 32-Ld Flat Pack 32-Ld Flat Pack 32-Ld Flat Pack 32-Ld Flat Pack 32-Ld Flat Pack 36-Ld Pin Grid Array 36-Ld Pin Grid Array 36-Ld Pin Grid Array 36-Ld Pin Grid Array 36-Ld Pin Grid Array 32-Ld Extended LCC 32-Ld Extended LCC 32-Ld Extended LCC 32-Ld Extended LCC 32-Ld Ceramic SOIC (Gull Wing) 32-Ld Ceramic SOIC (Gull Wing) 32-Ld Ceramic SOIC (Gull Wing) 32-Ld Ceramic SOIC (Gull Wing) 32-Ld Ceramic SOIC (Gull Wing) Wafer G36.760x760A G36.760x760A G36.760x760A G36.760x760A G36.760x760A PKG. DWG # F32.6 F32.6 F32.6 F32.6 F32.6 F32.6 F32.6 F32.6 F32.6 F32.6
2
FN8105.1 February 12, 2007
X28C010, X28HT010 Block Diagram
A8-A16 X Buffers Latches and Decoder 1Mbit EEPROM Array
A0-A7
Y Buffers Latches and Decoder
I/O Buffers and Latches
CE OE WE VCC VSS
Control Logic and Timing
I/O0-I/O7 Data Inputs/Outputs
Pin Descriptions
Addresses (A0-A16) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers, and is used to initiate read operations. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X28C010/X28HT010 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28C010/X28HT010. Back Bias Voltage (VBB) (X28HT010 only) It is required to provide -3V on pin 1. This negative voltage improves higher temperature functionality.
Pin Names
SYMBOL A0-A16 I/O0-I/O7 WE CE OE VCC VSS NC VBB* *VBB applies to X28HT010 only. DESCRIPTION Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect -3V
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C010/X28HT010 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms.
3
FN8105.1 February 12, 2007
X28C010, X28HT010
Page Write Operation
The page write feature of the X28C010/X28HT010 allows the entire memory to be written in 5 seconds. Page write allows two to two hundred fifty-six bytes of data to be consecutively written to the X28C010/X28HT010 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A8 through A16) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to two hundred fifty six bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s.
I/O DP TB 5 4 3 2 1 0
Reserved Toggle Bit DATA Polling
FIGURE 1. STATUS BIT ASSIGNMENT
DATA Polling (I/O7)
The X28C010/X28HT010 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C010/X28HT010, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Note: If the X28C010/X28HT010 is in the protected state, and an illegal write operation is attempted, DATA Polling will not operate.
Write Operation Status Bits
The X28C010/X28HT010 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1.
Toggle Bit (I/O6)
The X28C010/X28HT010 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.
DATA Polling I/O7
WE Last Write
CE
OE VIH I/O7 HIGH Z VOL
VOH X28C010 Ready An An An An
A0-A14
An
An
An
FIGURE 2. DATA POLLING BUS SEQUENCE
4
FN8105.1 February 12, 2007
X28C010, X28HT010
DATA Polling can effectively halve the time for writing to the X28C010/X28HT010. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine.
No
Write Data
Writes Complete?
Yes Save Last Data and Address
Read Last Address
IO7 Compare? Yes X28C010 Ready
No
FIGURE 3. DATA POLLING SOFTWARE FLOW
The Toggle Bit I/O6
WE Last Write
CE
OE
I/O6
VOH * VOL
HIGH Z
* X28C010 Ready
* Beginning and ending state of I/O6 will vary
FIGURE 4. TOGGLE BIT BUS SEQUENCE
5
FN8105.1 February 12, 2007
X28C010, X28HT010 Software Data Protection
Last Write
Load Accum From Addr N
The X28C010/X28HT010 offers a software controlled data protection feature. The X28C010/X28HT010 is shipped from Intersil with the software data protection NOT ENABLED: that is the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. The X28C010/X28HT010 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the X28C010/X28HT010 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device.
Compare Accum with Addr N
Compare Ok?
No
Yes
Ready
FIGURE 5. TOGGLE BIT SOFTWARE FLOW
Software Algorithm
Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figures 6 and 7 for the sequence. The three byte sequence opens the page write window enabling the host to write from one to two hundred fifty-six bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state.
The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28C010/X28HT010 memories that is frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit.
Hardware Data Protection
The X28C010/X28HT010 provides three hardware features that protect nonvolatile data from inadvertent writes. * Noise Protection--A WE pulse less than 10ns will not initiate a write cycle. * Default VCC Sense--All functions are inhibited when VCC is 3.5V. * Write inhibit--Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during powerup and power-down, maintaining data integrity.
6
FN8105.1 February 12, 2007
X28C010, X28HT010
Software Data Protection
VCC 0V Data Addr CE tBLC MAX WE AA 5555 55 2AAA A0 5555 Writes Ok Byte or Page (VCC)
tWC
Write Protected
FIGURE 6. TIMING SEQUENCE--BYTE OR PAGE WRITE
Write Data AA to Address 5555
Write Data 55 to Address 2AAA
Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the X28C010/X28HT010 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28C010/X28HT010 will be write protected during power-down and after any subsequent power-up. The state of A15 and A16 while executing the algorithm is don't care. Note: Once initiated, the sequence of write operations should not be interrupted.
Write Data A0 to Address 5555
Write Data XX to Any Address
Optional Byte/Page Load Operation
Write Last Byte Last Address
After tWC Re-Enters Data Protected State
FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA PROTECTION
7
FN8105.1 February 12, 2007
X28C010, X28HT010
Resetting Software Data Protection
VCC
Data Addr CE
AA 5555
55 2AAA
80 5555
AA 5555
55 2AAA
20 5555
tWC
Standard Operating Mode
WE
FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE
System Considerations
Write Data AA to Address 5555
Write Data 55 to Address 2AAA
Because the X28C010/X28HT010 is frequently used in large memory arrays, it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit, it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. Because the X28C010/X28HT010 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1F high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7F electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
Write Data 80 to Address 5555
Write Data AA to Address 5555
Write Data 55 to Address 2AAA
Write Data 20 to Address 5555
FIGURE 9. SOFTWARE SEQUENCE TO DEACTIVATE SOFTWARE DATA PROTECTION
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28C010/X28HT010 will be in standard operating mode. Note: Once initiated, the sequence of write operations should not be interrupted.
8
FN8105.1 February 12, 2007
X28C010, X28HT010
Active Supply Current vs. Ambient Temperature
18 VCC = 5V 16 ICC WR (mA)
14
12
10 -55 -10 +35 +80 +125 Ambient Temperature (C)
Standby Supply Current vs. Ambient Temperature
0.3 VCC = 5V 0.25 ISB (mA) 0.2 0.15 0.1 0.05 -55 -10 +35 +80 +125 Ambient Temperature (C)
ICC (RD) by Temperature Over Frequency
60 50 ICC RD (mA) 40 30 20 10 0 3 6 9 12 15 Frequency (MHz) 5.0 VCC -55C +25C +125C
9
FN8105.1 February 12, 2007
X28C010, X28HT010
Absolute Maximum Ratings
Temperature under bias X28C010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10C to +85C X28C010I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +135C X28C010M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +135C X28HT010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55C to +175C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on any pin with respect to VSS . . . . . . . . . . . . . . -1V to +7V D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300C
Recommended Operating Conditions
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C tp +85C Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55C to +125C Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V 10% High Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +175C
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions (above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Specifications
SYMBOL ICC ISB1 ISB2 ILI PARAMETER
Over the recommended operating conditions, unless otherwise specified. TEST CONDITIONS CE = OE = VIL, WE = VIH, All I/O's = Open, Address Inputs = 0.4V/2.4V Levels @ f = 5MHz CE = VIH, OE = VIL, All I/O's = Open, Other Inputs = VIH CE = VCC - 0.3V, OE = VIL, All I/O's = Open, Other Inputs = VCC VIN = VSS to VCC VIN = VSS to VCC (Note 2) MIN MAX 50 3 500 10 20 10 20 -1 (Note 2) -1 2 (Note 2) 2.2 0.8 0.6 VCC + 1 VCC + 1 0.4 0.5 2.4 2.6 200 UNIT mA mA A A A A A V V V V V V V V A
VCC Current (Active) (TTL Inputs) VCC Current (Standby) (TTL Inputs) VCC Current (Standby) (CMOS Inputs) Input Leakage Current
ILO
Output Leakage Current
VOUT = VSS to VCC, CE = VIH VOUT = VSS to VCC, CE = VIH (Note 2)
VlL (Note 1) Input LOW Voltage
VIH (Note 1) Input HIGH Voltage
VOL
Output LOW Voltage
IOL = 2.1mA IOL = 1mA (Note 2)
VOH
Output HIGH Voltage
IOH = -400A IOH = -400A
IBB NOTE:
Back Bias Current
VBB = -3V 10% (Note 2)
1. VIL min. and VIH max. are for reference only and are not tested. 2. X28HT010W
Power-Up Timing
SYMBOL tPUR (Note 3) tPUW (Note 3) PARAMETER Power-up to Read operation Power-up to Write operation TA = +25C, f = 1MHz, VCC = 5V PARAMETER Input/Output capacitance Input capacitance TEST CONDITIONS VI/O = 0V VIN = 0V MAX 10 10 UNIT pF pF MAX 100 5 UNIT s ms
Capacitance
SYMBOL CI/O (Note 3) CIN (Note 3) NOTE:
3. This parameter is periodically sampled and not 100% tested.
10
FN8105.1 February 12, 2007
X28C010, X28HT010
Endurance and Data Retention
PARAMETER Endurance Endurance Data Retention MIN 10,000 100,000 100 MAX UNIT Cycles per byte Cycles per page Years
A.C. Conditions of Test
Input pulse levels Input rise and fall times Input and output timing levels 0V to 3V 10ns 1.5V
Symbol Table
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
Mode Selection
CE L L H X X OE L H X L X WE H L X X H MODE Read Write Standby and Write Inhibit Write Inhibit Write Inhibit I/O DOUT DIN High Z -- -- POWER Active Active Standby -- --
Equivalent A.C. Load Circuit
5V 1.92k Output 1.37k 100pF
AC Electrical Specifications
Over the recommended operating conditions, unless otherwise specified. X28C010-12 X28C010-15 MIN MAX X28C010-20, X28HT010W MIN MAX X28C010-25 MIN MAX UNIT
SYMBOL READ CYCLE LIMITS tRC tCE tAA tOE tLZ (Note 4) tOLZ (Note 4) tHZ (Note 4) tOHZ (Note 4) tOH
PARAMETER
MIN
MAX
Read cycle time Chip enable access time Address access time Output enable access time CE LOW to active output OE LOW to active output CE HIGH to high Z output OE HIGH to high Z output Output hold from address change
120 120 120 50 0 0 50 50 0
150 150 150 50 0 0 50 50 0
200 200 200 50 0 0 50 50 0
250 250 250 50 0 0 50 50 0
ns ns ns ns ns ns ns ns ns
11
FN8105.1 February 12, 2007
X28C010, X28HT010
Read Cycle
tRC Address tCE CE tOE OE VIH WE tOLZ tLZ Data I/O HIGH Z Data Valid tAA tOH Data Valid tHZ tOHZ
NOTE: 4. tLZ min.,tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
Write Cycle Limits
SYMBOL tWC (Note 5) tAS tAH tCS tCH tCW tOES tOEH tWP tWPH tDV tDS tDH tDW tBLC Write cycle time Address setup time Address hold time Write setup time Write hold time CE pulse width OE HIGH setup time OE HIGH hold time WE pulse width WE HIGH recovery Data valid Data setup Data hold Delay to next write Byte load cycle 50 0 10 0.2 100 0 50 0 0 100 10 10 100 100 1 PARAMETER MIN MAX 10 UNIT ms ns ns ns ns ns ns ns ns ns s ns ns s s
12
FN8105.1 February 12, 2007
X28C010, X28HT010
WE Controlled Write Cycle
tWC Address tAS tCS CE tAH tCH
OE tOES tWP WE tDV Data In tDS Data Out HIGH Z Data Valid tDH tWPH tOEH
NOTE: 5. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to complete internal write operation.
CE Controlled Write Cycle
tWC Address tAS CE tOES OE tOEH tCS WE tDV Data In tDS Data Out HIGH Z Data Valid tDH tCH tWPH tAH tCW
13
FN8105.1 February 12, 2007
X28C010, X28HT010
Page Write Cycle
OE (Note 5)
CE tWP WE tWPH tBLC
Address* (Note 7)
I/O Byte 0 Byte 1 Byte 2 Byte n Byte n+1
Last Byte Byte n+2 tWC *For each successive write within the page write operation, A8-A16 should be the same or writes to an unknown address could occur.
NOTES: 6. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. 7. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing.
DATA Polling Timing Diagram (Note 8)
Address An An An
CE
WE tOEH tOES
OE tDW I/O7 DIN = X DOUT = X tWC DOUT = X
14
FN8105.1 February 12, 2007
X28C010, X28HT010
Toggle Bit Timing Diagram
CE
WE tOEH OE tDW I/O6 HIGH Z * tWC * I/O6 beginning and ending state will vary. * tOES
NOTE: 8. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
15
FN8105.1 February 12, 2007
X28C010, X28HT010 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F32.6 MIL-STD-1835 GDIP1-T32 (D-16, CONFIGURATION A) 32 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c c1 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.500 MAX 0.232 0.026 0.023 0.065 0.045 0.018 0.015 1.690 0.610 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.70 MAX 5.92 0.66 0.58 1.65 1.14 0.46 0.38 42.95 15.49 2.54 BSC 15.24 BSC 7.62 BSC 3.18 0.38 0.13 90 32 5.08 1.52 105 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 8/06
E
eA
D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.600 BSC 0.300 BSC 0.125 0.015 0.005 90 32 0.200 0.060 105 0.015 0.030 0.010 0.0015
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
16
FN8105.1 February 12, 2007
X28C010, X28HT010 Packaging Information
32-Lead Ceramic Flat Pack Type F
1.228 (31.19) 1.000 (25.40) Pin 1 Index 1 32
0.019 (0.48) 0.015 (0.38)
0.050 (1.27) BSC 0.830 (21.08) Max.
0.045 (1.14) Max. 0.005 (0.13) Min.
0.007 (0.18) 0.004 (0.10) 0.370 (9.40) 0.270 (6.86)
0.440 0.430 (10.93)
0.120 (3.05) 0.090 (2.29)
0.347 (8.82) 0.330 (8.38) 0.030 (0.76) Min.
0.026 (0.66) Min.
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
17
FN8105.1 February 12, 2007
X28C010, X28HT010 Packaging Information
32-Pad Stretched Ceramic Leadless Chip Carrier Package Type N
0.300 BSC 0.035 x 45 Ref. Detail A Pin 1 0.085 0.010 Detail A 0.400 BSC 0.025 0.003 0.005/0.015 0.006/0.022
0.050 0.005
0.050 BSC
0.020 (1.02) x 45 Ref. Typ. (3) Plcs.
0.450 0.008 0.458 Max. 0.060/0.120
0.700 0.010
0.708 Max.
Pin #1 Index Corner
NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: 1% NLT0.005 (0.127)
18
FN8105.1 February 12, 2007
X28C010, X28HT010 Packaging Information
32-Lead Ceramic Small Outline Gull Wing Package Type R
0.060 Nom. See Detail "A" For Lead Information 0.340 0.007 0.165 Typ.
0.020 Min. 0.015 R Typ.
0.035 Typ.
0.015 R Typ. Detail "A"
0.035 Min.
0.019 0.015
0.050" Typical 0.050" Typical
0.830 Max.
0.750 0.005
0.560" Typical
0.050
FOOTPRINT
0.030" Typical 32 Places
0.440 Max. 0.560 Nom.
NOTES: 1. ALL DIMENSIONS IN INCHES 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
19
FN8105.1 February 12, 2007
X28C010, X28HT010 Packaging Information
36 Lead Ceramic Pin Grid Array Package Package Code G36.760x760A
15 13 12 10 8 6 Typ. 0.180 (.010) (4.57 .25) 4 Corners 14 11 9 7 5 4
17 16
19 18
21 20
22 A 23 25 27 29 24 26 A 28 30 31 Typ. 0.100 (2.54) All Leads 0.050 (1.27) NOTE: Leads 5, 14, 23, & 32 0.008 (0.20)
2 3
36 1
34 35
32 33
Typ. 0.180 (.010) (4.57 .25) 4 Corners Pin 1 Index
0.120 (3.05) 0.100 (2.54) 0.072 (1.83) 0.062 (1.57)
0.770 (19.56) 0.750 (19.05) SQ A A 0.020 (0.51) 0.016 (0.41)
0.185 (4.70) 0.175 (4.45)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 20
FN8105.1 February 12, 2007

▲Up To Search▲

Price & Availability of X28HT010W

	To Download X28HT010W Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .